A typical and basic resettable latch circuit is shown in FIG. 1a and will be used to illustrate various drawbacks of prior art latch circuits incorporating a reset feature. Generally, the circuit of FIG. 1a is comprised of three portions: follow circuit 2, hold circuit 3, and output circuit 4. Follow circuit 2 receives data signals Data.sub.in and Data.sub.in. Upon enablement of follow circuit 2 by a high clock signal CLK, follow circuit 2 applies corresponding signals, to output circuit 4, which then generates the appropriate output signals, Data.sub.out and Data.sub.out. The function of hold circuit 3 is to maintain the state of Data.sub.out and Data.sub.out while clock signal CLK is low, i.e., when CLK is high. Therefore, the states of Data.sub.out and Data.sub.out will be fixed until the states of Data.sub.in and Data.sub.in change and CLK goes high. The function of output circuit 4 is to level shift the signals generated by follow circuit 2 and hold circuit 3 in order to provide the desired level of Data.sub. out and Data.sub.out to a subsequent stage.
A reset signal RST may be concurrently applied to follow circuit 2 and hold circuit 3 to reset Data.sub.out to a logical zero and Data.sub.out to a logical one. The latch will be in its reset state until reset signal RST is removed and clock signal CLK is high. The drawback in the configuration of the resettable latch circuit of FIG. 1a, as will be seen in detail below, is that reset signal RST must have a high state level which is higher than the high state level of Data.sub.in in order for reset signal RST to override a high Data.sub.in signal. FIG. 1b shows a diagram of the required high and low voltage levels of clock signal CLK, Data.sub.in, and reset signal RST between the range of zero volts and supply voltage V.sub.cc. Since a larger Data.sub.in swing would make follow circuit 2 less affected by noise, it is advantageous to eliminate the need for the reset signal to use up a portion of the zero to V.sub.cc voltage range to allow the Data.sub.in signal to have a larger voltage swing. The circuit of FIG. 1a and another prior art latch circuit will now be described in detail so that the above-described drawback and other drawbacks of prior art resettable latch circuits will be made clear.
In FIG. 1a, constant current source 10 is coupled to the emitters of transistors Q1 and Q5 forming a differential pair. The configuration of this differential pair operates such that when clock signal CLK is high, all current supplied by current source 10 will flow through transistor Q1. The collector of transistor Q1 is coupled to a differential pair configuration comprising transistor Q2 and transistors Q3 and Q4 coupled in parallel, wherein data signal Data.sub.in is coupled to the base of transistor Q2, Data.sub.in is coupled to the base of transistor Q3, and reset signal RST is coupled to the base of transistor Q4. Thus, when clock signal CLK is high and Data.sub.in is sufficiently high to turn on transistor Q2 and bias transistor Q1 in its active mode, current supplied by current source 10 flows through transistor Q2 and pulls down node 1 (the collector of transistor Q2) to a low level. Meanwhile, Data.sub.in, being at a low level, renders transistor Q3 nonconductive. When reset signal RST is low and node 1 is low, transistor Q10, whose base is coupled to node 1 and whose collector is coupled to +V.sub.cc, will be in a low state. Since node 1 is low, the emitter of transistor Q10, which is coupled to the Data.sub.out terminal and current source 14, is also low. Since transistors Q3 and Q4 are off, node 2 (the common collectors of transistors Q4 and Q3) will be high. Transistor Q9, whose base is coupled to node 2 and whose collector is coupled to +V.sub.cc, will be in a high state, pulling up to a high level the Data.sub.out terminal coupled to the emitter of transistor Q9 and to current source 12. Current sources 12 and 14 act to pull a constant current through transistors Q9 and Q10 and resistors R3 and R4. Thus, as seen, a high Data.sub.in signal produces a high Data.sub.out signal and a low Data.sub.out signal. It is easily seen that a high Data.sub.in signal produces a low Data.sub.out signal and a high Data.sub.out signal.
If clock signal CLK is at a high level and reset signal RST is driven high, transistor Q4 would be turned on even if Data.sub.in is high, since reset signal RST is higher than a high state Data.sub.in signal. Thus, all current would flow through transistor Q4, causing node 2 to be driven low and node 1 to be driven high, thus forcing Data.sub.out low and Data.sub.out high.
When clock signal CLK goes low, the transistors comprising follow circuit 2 are disabled and have no effect on the levels at nodes 1 and 2. However, when clock signal CLK goes low, clock signal CLK goes high, turning on transistor Q5 and enabling hold circuit 3. The collector of transistor Q5 is coupled to a differential pair configuration comprising transistor Q6 and transistor Q7 and Q8 in parallel. The base of transistor Q6 is coupled to the Data.sub.out terminal through resistor R3, and the base of transistor Q7 is coupled to the Data.sub.out terminal through resistor R4. Reset signal RST is coupled to the base of transistor Q8. Resistors R3 and R4 are to set the voltage levels at the bases of transistors Q6 and Q7 to approximately the levels at the bases of transistors Q6 and Q7 to approximately the levels of Data.sub.in and Data.sub.in so that these levels will be compatible with the high CLK signal and the reset signal RST levels. Current sources 12 and 14 fix the voltage drop across resistors R3 and R4. The operation of hold circuit 3 is virtually identical to the operation of follow circuit 2 except that the inputs to transistors Q6 and Q7 now correspond to the states of Data.sub.out and Data.sub.out, respectively. Thus, when Data.sub.out is high during a high CLK signal, transistor Q6 will be turned on, driving node 1 low and holding transistor Q10 in the low state. Since transistor Q10 is in the low state, Data.sub.out is driven low. And, since Data.sub.out is low, transistor Q7, whose base is coupled to Data.sub.out through resistor R4, is off allowing node 2 to be in the high state. A high node 2 keeps transistor Q9 in the high state which keeps Data.sub.out high. Hence, Data.sub.out and Data.sub.out are held during the time CLK is high.
The high CLK voltage must be sufficiently below the low Data.sub.in voltage for transistor Q1 to have sufficient collector voltage to be biased into its active mode, and the high RST voltage must be sufficiently above the high Data.sub.in voltage in order to prevent transistor Q2 from turning on when a high RST signal is applied to the base of transistor Q4. These voltage relationships are shown in FIG. 1b. As previously stated, the margin between the high RST voltage and the high Data.sub.in voltage uses up part of the already limited voltage range between zero volts and +V.sub.cc which could otherwise be used to increase the swing of Data.sub.in or reduce the required V.sub.cc. Additionally, the reset circuitry of the latch of FIG. 1a requires a modification of the basic latch circuitry (i.e., adding transistors Q4 and Q8, and changing the level of Data.sub.in and the voltages at the bases of transistors Q7 and Q6). Further, various gate delays are incurred between the application of reset signal RST and the resetting of Data.sub.out and Data.sub. out.
In contrast to the circuit of FIG. 1a, FIG. 2a shows a prior art resettable latch circuit which uses single ended circuitry and whose reset signal does not limit the voltage swing of input data signal Data.sub.in. The schematic of FIG. 2a is an actual schematic of the MECL III master-slave type D flip-flop (MC 1670) by Motorola. A master-slave flip-flop overcomes any unpredictable behavior of an edge triggered type flip-flop for slow-rising clock input pulses. In FIG. 2a, the master side of the master-slave flip-flop receives (follows) Data.sub.in on the trailing edge of clock pulse CLK and applies signals representing Data.sub.out and Data.sub.out, corresponding to the levels at node 4 and node 2, respectively, to the slave side. On the leading edge of the next clock pulse the master side holds Data.sub.out and Data.sub.out. The slave side follows the held data from the master side, i.e., Data.sub.out and Data.sub.out, on the same leading edge of clock pulse CLK but at a slightly delayed time and provides data signals to an output stage which, in turn, provides Data'.sub.out and Data' .sub.out corresponding to Data.sub.out and Data.sub.out, respectively. The sleeve side then holds the data on the trailing edge of the clock pulse. FIG. 2b shows the various functions of the master and slave sides during a clock cycle.
The circuit of FIG. 2a uses differential logic similar to that used in FIG. 1a except that the voltages applied to the input terminals, such as Data.sub.in, are applied to one transistor of the differential pair while the other transistor of the differential pair has applied to its control terminal a fixed reference voltage instead of, for example, Data.sub.in . This configuration requires the voltage swing of the Data.sub.in signal to be twice as great as the Data.sub.in signal in FIG. 1a in order to provide the same difference in voltage at the control terminals of the differential pair. Thus, generally speaking, the circuit of FIG. 2a will not function as well at lower V.sub.cc 's, since the aggregate of the various larger voltage swings must fit into a restricted voltage range.
Detailed operation of the circuit of FIG. 2a is as follows. Assuming a high data signal Data.sub.in is applied to the Data.sub.in terminal and, hence, to the base of transistor 1Q4, and low clock signal CLK is applied to the CLK terminal, a low signal will thus be applied to the base of transistor 1Q2, and transistor 1Q3 will be turned on by reference voltage REF1, enabling the follow portion of the master side of the flip-flop. Because of the high Data.sub.in signal at the base of transistor 1Q4, the collector of transistor 1Q4, node 1, will be low and, since node 1 is coupled to the base of transistor 1Q11, the emitter of transistor 1Q11 will be low. Since the emitter of transistor 1Q11 is low, node 2, coupled to the emitter of transistor 1Q11 through resistor R2, will also be low. The signal at node 2 represents Data.sub.out and is applied to the follow portion of the sleeve side of the flip-flop. The high Data.sub.in signal, being higher then REF2, makes transistor 1Q9 nonconductive and, hence, its collector, node 5, is at a high voltage. This high voltage is coupled to the base of transistor 1Q10 which conducts and pulls node 4, coupled to the emitter of transistor 1Q10 through resistor R3, up to a high level. The signal at node 4 represents Data.sub.out and is applied to the follow portion of the slave side of the flip-flop.
When CLK goes high, transistor 1Q2 turns on, since CLK is higher than REF1, and the levels on nodes 2 and 4 are held by transistors 1Q6 and 1Q7 having inputs into their bases of the voltages at nodes 4 and 5, respectively. Thus, the master side of the flip-flop follows Data.sub.in when clock signal CLK is low and holds Data.sub.out and Data.sub.out when clock signal CLK goes high.
The slave side of the flip-flop receives the held output of the master side via transistors 2Q9 and 2Q4 when clock signal CLK is high and applies corresponding signals on nodes 5 and 6 to an output stage comprising transistors 2Q14 and 2Q15. The output stage provides level shifted signals Data'.sub.out and Data'.sub.out, corresponding to the signals on nodes 5 and 6, respectively. The data in the slave side is held by transistors 2Q7 and 2Q6 when CLK once again goes low. The master section then follows a new Data.sub.in bit applied to the Data.sub.in terminal.
The reset operation of the flip-flop of FIG. 2a differs from the operation of the reset FIG. 1a in a variety of ways. In the flip-flop of FIG. 2a, a high reset signal RST performs the same function as a high clock signal by turning on transistors 1Q2 and 2Q2. Thus, when reset signal RST is high, the functions of the master and slave sides of the flip-flop will operate as if clock signal CLK itself was high, i.e., the master holds and the slave follows. Additionally, reset signal RST is applied to the bases of transistors 1Q8 and 2Q8. Transistor 1Q8 forms part of the hold portion of the master side of the flip-flop and is in parallel with transistor 1Q7, transistor 1Q7 being the transistor which conducts during the hold function when Data.sub.out is high and RST is low. Thus, when reset signal RST is high, enabling the hold portion of the master side by turning on transistor 1Q2, the high reset signal RST also turns on transistor 1Q8 which performs the same function as transistor 1Q7 when Data.sub.out is high. The low voltage at the collector of transistor 1Q8 forces transistor 1Q10 to the low state and, hence, the emitter of transistor 1Q10, as well as node 4, are low. Since nodes 4 and 2 are at opposite states, the voltage at node 2 is high. Thus, a high signal is coupled to the base of transistor 2Q9 and a low signal is coupled to the base of transistor 2Q4 in the slave side of the flip-flop. Since the reset signal RST is high, transistor 2Q2 is on and current flows through transistor 2Q9. The low signal at the collector of transistor 2Q9 is applied to the base of output transistor 2Q14, forcing transistor 2Q14 to the low state and signalling a low Data'.sub.out. Necessarily, the collector of transistor 2Q4 is now at a high state and forces transistor 2Q15 to the high state, signalling a high Data'.sub.out.
When reset signal RST is removed and clock signal CLK is low, normal operation of the master-slave flip-flop resumes. In the flip-flop of FIG. 2a, the level of reset signal RST need only be higher than the highest level of the voltages at the bases of transistors 1Q7 and 1Q6 in the master side of the flip-flop. Since the levels of the voltages applied to the bases of transistors 1Q6 and 1Q7 are generated within the flip-flop (e.g., by transistors 1Q10 and 1Q11 in conjunction with resistors R3 and R2, the reset level does not affect the level of Data.sub.in or the CLK level as it did in the circuit of FIG. 1a. In FIG. 2a, the reset level should be identical to the CLK level.
The circuit of FIG. 2a has overcome the problem regarding the extra level needed for a reset function, however, FIG. 2a only teaches how to solve this problem using circuits with single ended logic wherein one transistor of a differential pair is coupled to a fixed reference voltage (e.g., REF1, REF3). The disadvantage of single ended logic has been discussed previously. Another drawback with the reset operation in the circuit of FIG. 2a is the added gate delays incurred when a reset signal goes high, e.g., the delay through transistors 2Q8, 2Q10, 2Q6, and 2Q11. Further, three extra transistors, 1Q18, 1Q8, and 2Q8, are required to implement the reset function. It is therefore desirable to construct a circuit using differential logic wherein the level of the reset signal does not limit the range of the data input signal or the clock signal, wherein the reset function can be implemented into a latch circuit with a minimum number of additional components, and wherein the latch does not incur gate delay in its reset operation.